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1 s2060 gigabit ethernet transceiver march 7, 2001 / revision h s2060 ? device specification gigabit ethernet transceiver features ? operating rate ? 1250 mhz (gigabit ethernet) line rates ? half and full vco output rates ? functionally compliant ieee 802.3z gigabit ethernet standard ? transmitter incorporating phase-locked loop (pll) clock synthesis from low speed reference ? receiver pll provides clock and data recovery ? 10-bit parallel ttl compatible interface ? low-jitter serial lvpecl compatible interface ? local loopback ? single +3.3 v supply, 620 mw power dissipation ? 64 pqfp or tqfp package ? continuous downstream clocking from receiver ? drives 30 m of twinax cable directly applications ? workstation ? frame buffer ? switched networks ? data broadcast environments ? proprietary extended backplanes general description the s2060 transmitter and receiver chip facilitates high speed serial transmission of data over fiber op- tic, coax, or twinax interfaces. the device conforms to the requirements of the ieee 802.3z gigabit ethernet specification, and runs at 1250.0 mbps data rates with an associated 10-bit data word. the chip provides parallel-to-serial and serial-to-par- allel conversion, clock generation/recovery, and framing for block encoded data. the on-chip transmit pll synthesizes the high-speed clock from a low- speed reference. the on-chip receive pll performs clock recovery and data re-timing on the serial bit stream. the transmitter and receiver each support differential lvpecl compatible i/o for copper or fi- ber optic component interfaces with excellent signal integrity. local loopback mode allows for system di- agnostics. the chip requires a +3.3 v power supply and dissipates typically 620 mw. the s2060 can be used for a variety of applications including gigabit ethernet, serial backplanes, and proprietary point-to-point links. figure 1 shows a typical configuration incorporating the chip. figure 1. system block diagram s2060 gigabit ethernet controller optical tx optical rx optical tx optical rx s2060 gigabit ethernet controller
2 s2060 gigabit ethernet transceiver march 7, 2001 / revision h s2060 overview the s2060 transmitter and receiver provide serial- ization and deserialization functions for block en- coded data to implement a gigabit ethernet interface. the s2060 functional block diagram is de- picted in figure 2. the sequence of operations is as follows: transmitter 1.10-bit parallel input 2. parallel-to-serial conversion 3. serial output receiver 1. clock and data recovery from serial input 2. serial-to-parallel conversion 3. frame detection 4. 10-bit parallel output the 10-bit parallel data input to the s2060 should be from a dc-balanced encoding scheme, such as the 8b/10b transmission code, in which information to be transmitted is encoded 8 bits at a time into 10-bit trans- mission characters 1 . for reference, table 1 shows the mapping of the parallel data to the 8b/10b codes. loop back local loopback provides a capability for performing off-line testing. this is useful for ensuring the integ- rity of the serial channel before enabling the trans- mission medium. it also allows for system diagnostics. figure 2. functional block diagram e t y b a t a d ] 9 : 0 [ x r r o ] 9 : 0 [ x t 0123456789 b 0 1 / b 8 n o i t a t n e s e r p e r c i t e b a h p l a abcdei fghj table 1. data mapping to 8b/10b alphabetic representation 1. a.x. widmer and p.a. franaszek, "a byte oriented dc bal- anced (0,4) 8b/10b transmission code," ibm research report rc 9391, may 1982. fifo (4 x 10) shift register 10 10 pll clock recovery w/ lock detect shift register d control logic comma detect logic dq 10 tx[0:9] tbc rxp rxn ewrap -lck_ref en_cdet rbc0 rbc1 com_det rx[0:9] txn txp s2060 raten 2:1 pll clock multiplier w/ lock detect f0 = f1 x 10
3 s2060 gigabit ethernet transceiver march 7, 2001 / revision h transmitter description the s2060 transmitter accepts 10-bit parallel input data and serializes it for transmission over fiber optic or coaxial cable media. the chip is fully compatible with the ieee 802.3z gigabit ethernet standard, and supports the gigabit ethernet data rate of 1250.0 mbps. the s2060 uses a pll to generate the serial rate transmit clock. the transmitter runs at 10 times the tbc input clock, and operates in either full rate or half rate mode. at the full vco rate the transmitter runs at 1.25 ghz, while in half rate mode it operates at 625 mhz. parallel-to-serial conversion the parallel-to-serial converter takes in 10-bit wide data from the input latch and converts it to a serial data stream. parallel data is latched into the trans- mitter on the positive going edge of tbc. the data is then clocked into the serial output shift register. the shift register is clocked by the internally generated bit clock which is 10x the tbc input frequency. tx[0] is transmitted first. transmit byte clock (tbc) the transmit byte clock input (tbc) must be sup- plied from a clock source with 100 ppm tolerance to assure that the transmitted data meets the gigabit ethernet frequency limits. the internal serial clock is frequency locked to tbc (125.00 mhz). tbc may be 62.5 mhz or 125 mhz, determined by the state of the raten input. operating rates are shown in table 2. transmit latency the average transmit latency is 4 byte times. n e t a r t u p n i l e l l a r a p ) s p b m ( e t a r) s p b m ( e t a r ) s p b m ( e t a r ) s p b m ( e t a r) s p b m ( e t a r y c n e u q e r f c b t ) z h m () z h m ( ) z h m ( ) z h m () z h m ( t u p t u o l a i r e s ) s p b g ( e t a r) s p b g ( e t a r ) s p b g ( e t a r ) s p b g ( e t a r) s p b g ( e t a r 05 2 15 2 15 2 . 1 15 . 2 65 . 2 65 2 6 . 0 table 2. operating rates
4 s2060 gigabit ethernet transceiver march 7, 2001 / revision h receiver description whenever a signal is present, the receiver attempts to recover the serial clock from the received data stream. the s2060 searches the serial bit stream for the occurrence of a positive polarity comma sync pattern (0011111xxx positive running disparity) to perform word synchronization. once synchronization on both bit and word boundaries is achieved, the receiver provides the decoded data on its parallel outputs. clock recovery function clock recovery is performed on the input data stream. a simple state machine in the clock recovery macro decides whether to acquire lock from the se- rial data input or from the reference clock. the deci- sion is based upon the frequency and run length of the input serial data. the lock to reference frequency criteria ensure that the s2060 will respond to variations in the serial data input frequency (as compared to the reference fre- quency). the new lock state is dependent upon the current lock state, as shown in table 3. the run- length criteria ensure that the s2060 will respond ap- propriately and quickly to a loss of signal. the run- length checker flags a condition of consecutive ones or zeros across 12 parallel words. thus, 119 or less consecutive ones or zeros does not cause signal loss, 129 or more causes signal loss, and 120 C 128 may or may not, depending on how the data aligns across byte boundaries. if both the off-frequency detect test and the run-length test is satisfied, the cru will at- tempt to lock to the incoming data. in any transfer of pll control between the serial data and the reference clock, the rbc0 and rbc1 remain phase continuous and glitch free, assuring the integrity of downstream clocking. reference clock input the reference clock must be provided from a low jitter clock source. the frequency of the received data stream must be within 400 ppm of the reference clock to ensure reliable locking of the receiver pll. a single reference clock is provided to both the transmit and receive pll's. data output the s2060 provides either framed or unframed par- allel output data, determined by the state of en_cdet. with en_cdet held active, the s2060 will detect and align to the 8b/10b comma codeword anywhere in the data stream. when en_cdet is inactive, no attempt is made to syn- chronize on any particular incoming character. the s2060 will achieve bit synchronization within 250 bit times and begin to deliver unframed parallel output data words whenever it has received full transmis- sion words. upon change of state of the en_cdet input, the com_det output response will be de- layed by a maximum of 3 byte times. k c o l t n e r r u c e t a t se t a t s e t a t s e t a t se t a t s y c n e u q e r f l l p ) c b t . s v () c b t . s v ( ) c b t . s v ( ) c b t . s v () c b t . s v ( e t a t s k c o l w e n d e k c o l m p p 8 8 4 d e k c o l n u d e k c o l n u m p p 4 4 2 d e k c o l n u table 3. lock to reference frequency criteria
5 s2060 gigabit ethernet transceiver march 7, 2001 / revision h the com_det output signal is active whenever en_cdet is active and the comma control charac- ter is present on the rx[0:9] parallel data outputs. the com_det output signal will be inactive at all other times. parallel output clock rate and data stretching the s2060 supports both full rate and half rate out- puts, selected via the raten input. table 4 shows the operating rate scenarios. when raten is inac- tive, a data clock is provided on rbc1 at the data rate. data should be clocked on the rising edge of rbc1. when raten is active the device is in full rate mode, and complementary ttl clocks are pro- vided on the rbc0 and rbc1 outputs at 1/2 the data rate as required by the gigabit ethernet stan- dard. data is clocked on the rising edges of both rbc0 and rbc1. see figures 11 and 12. n e t a r t u p n i l a i r e s ) s p b g ( e t a r) s p b g ( e t a r ) s p b g ( e t a r ) s p b g ( e t a r) s p b g ( e t a r 0 c b r ) z h m () z h m ( ) z h m ( ) z h m () z h m ( 1 b c r ) z h m () z h m ( ) z h m ( ) z h m () z h m ( l e l l a r a p e t a r t u p t u oe t a r t u p t u o e t a r t u p t u o e t a r t u p t u oe t a r t u p t u o ) s p b m () s p b m ( ) s p b m ( ) s p b m () s p b m ( 05 2 . 15 . 2 65 . 2 65 2 1 15 2 6 .a / n5 . 2 65 . 2 6 table 4. operating rates fibre channel and gigabit ethernet standards re- quire that the comma sync character appears on the rising edge of the rbc1 signal. in full rate mode the phase of the data is adjusted such that this re- quirement is met. no alignment is necessary when the s2060 is operating in half rate mode since the output clock frequency is equal to the parallel word rate (raten inactive). in ethernet applications it is illegal for multiple con- secutive comma characters to be generated. how- ever, multiple consecutive comma characters can occur in serial backplane applications. the s2060 is able to operate properly when multiple consecutive comma characters are received: after the first comma is detected and aligned, the rbc0/rbc1 clock operates without glitches or loss of cycles. additionally, com_det stays high while multiple commas are being output. receive latency the average receive latency is 8 byte times.
6 s2060 gigabit ethernet transceiver march 7, 2001 / revision h table 5. pin description and assignment e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d ] 9 [ x t ] 8 [ x t ] 7 [ x t ] 6 [ x t ] 5 [ x t ] 4 [ x t ] 3 [ x t ] 2 [ x t ] 1 [ x t ] 0 [ x t l t t v li3 1 2 1 1 1 9 8 7 6 4 3 2 e h t n o n i d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . a t a d t i m s n a r t . t s r i f d e t t i m s n a r t s i ] 0 [ x t . c b t f o e g d e g n i s i r c b tl t t v li2 2k c o l c l l p e h t o t t u p n i k c o l c e c n e r e f e r . k c o l c e t y b t i m s n a r t . 0 1 y b d e d i v i d e t a r t i b e h t s i c b t f o y c n e u q e r f e h t . r e i l p i t l u m o t k c o l c o c v e h t s e c a l p e r c b t , e v i t c a s i n e t s e t n e h w l a t s y r c a y b d e i l p p u s e b d l u o h s c b t . t s e t y r o t c a f e t a t i l i c a f o t s e t a l s n a r t y l t c e r i d e n i l s i h t n o r e t t i j e c n i s e c n e r e f e r d e l l o r t n o c . a t a d t u p t u o e h t n o r e t t i j n e t a rl t t v li4 1e h t r o f s ' l l p e h t s e r u g i f n o c l a n g i s s i h t . w o l e v i t c a . t c e l e s e t a r 2 / 1 n i s i e c i v e d e h t , e v i t c a n i n e h w . y c n e u q e r f c b t e t a i r p o r p p a . e d o m e t a r l l u f n i s i e c i v e d e h t , e v i t c a n e h w . e d o m e t a r . 4 d n a 2 s e l b a t e e s t e d c _ n el t t v li4 2s e l b a n e , e v i t c a n e h w . h g i h e v i t c a . t c e t e d a m m o c e l b a n e e m a r f d r o w e h t t e s o t n r e t t a p c n y s a m m o c e h t f o n o i t c e t e d d e t a e r t s i a t a d , e v i t c a n i n e h w . w o l l o f o t a t a d e h t r o f y r a d n u o b . d e m a r f n u s a p a r w el t t v li9 1s t u p t u o a t a d l a i r e s r e t t i m s n a r t e h t , e v i t c a n e h w . p a r w e l b a n e e r a n / p x t . s t u p n i a t a d l a i r e s r e v i e c e r e h t o t d e t u o r y l l a n r e t n i e r a l a i r e s n / p x r e h t , e v i t c a n i n e h w . e t a t s s i h t n i ) 1 c i g o l ( c i t a t s . ) n o i t a r e p o l a m r o n ( d e t c e l e s e r a s t u p n i p x r n x r . f f i d l c e p v l i4 5 2 5 a t a d l a i r e s e v i e c e r l c e p v l ) . d e l p u o c y l e v i t i c a p a c y l l a n r e t x e ( . e v i t a g e n s i n x r , t u p n i l a i t n e r e f f i d e v i t i s o p e h t s i p x r . s t u p n i . v 3 . 1 - c c v o t d e s a i b y l l a n r e t n i f e r _ k c l -l t t v li7 2e h t , n e p o r o e v i t c a n i n e h w . t u p n i e c n e r e f e r o t k c o l . w o l e v i t c a . ) n o i t a r e p o l a m r o n ( a t a d g n i m o c n i e h t o t k c o l l l i w l l p e v i e c e r . t u p n i c b t e h t o t k c o l o t d e c r o f s i l l p e v i e c e r e h t , e v i t c a n e h w
7 s2060 gigabit ethernet transceiver march 7, 2001 / revision h note: all ttl inputs have internal 15 k w pull-up networks. e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d ] 9 [ x r ] 8 [ x r ] 7 [ x r ] 6 [ x r ] 5 [ x r ] 4 [ x r ] 3 [ x r ] 2 [ x r ] 1 [ x r ] 0 [ x r l t t v lo4 3 5 3 6 3 8 3 9 3 0 4 1 4 3 4 4 4 5 4 s u b s i h t n o a t a d l e l l a r a p , t u p t u o e t a r l l u f r o f . s t u p t u o a t a d e v i e c e r t s r i f e h t s i ] 0 [ x r . 1 c b r d n a 0 c b r f o s e g d e g n i s i r e h t n o d i l a v s i . d e v i e c e r t i b 1 c b r 0 c b r l t t v lo0 3 1 3 l e l l a r a p , e d o m e t a r l l u f n i . s k c o l c e t y b e v i e c e r y r a t n e m e l p m o c e e s ( 1 c b r d n a 0 c b r f o s e g d e g n i s i r e h t n o d i l a v s i a t a d e v i e c e r e h t n o d i l a v s i a t a d t u p t u o , e t a r f l a h r o f . ) m a r g a i d g n i m i t , 8 e r u g i f . 4 e l b a t e e s . 1 c b r f o e g d e g n i s i r t e d _ m o cl t t v lo7 4, e v i t c a s i t e d c _ n e n e h w . h g i h e v i t c a . t c e t e d a m m o c e h t n o t n e s e r p s i r e t c a r a h c c n y s e h t t a h t s e t a c i d n i t e d _ m o c c n y s a m m o c e h t f o n o i t c e t e d n o p u . ] 9 : 0 [ x r s t i b s u b l e l l a r a p d i l a v s i a t a d t u p t u o s i h t ) y t i r a l o p e v i t i s o p x x x 1 1 1 1 1 0 0 ( r e t c a r a h c k c o l c 1 c b r e n o r o f e v i t c a s n i a m e r d n a 1 c b r f o e g d e g n i s i r e h t n o e v i t c a n i d l e h s i t e d _ m o c , e v i t c a n i s i t e d c _ n e n e h w . d o i r e p e h t , t u p n i t e d c _ n e e h t f o e t a t s f o e g n a h c n o p u . ) 0 c i g o l ( 3 f o m u m i x a m a y b d e y a l e d e b l l i w e s n o p s e r t u p t u o t e d _ m o c . s e m i t e t y b p x t n x t . f f i d l c e p v l o2 6 1 6 p x t , h g i h n x t ( c i t a t s e r a s e n i l e s e h t . a t a d l a i r e s t i m s n a r t , h g i h n x t ( c i t a t s e r a s e n i l e s e h t . e v i t c a s i p a r w e n e h w ) h g i h e r a s t u p t u o e s e h t , p u t r a t s n o p u . e v i t c a s i t s r x t n e h w ) w o l p x t o t d e k c o l s a h l l p x t e h t l i t n u ) w o l p x t , h g i h n x t ( c i t a t s d l e h 0 5 1 e v i r d n a c t u p t u o h c a e . k c o l c e c n e r e f e r e h t w . d n u o r g o t s n i p c i f i c e p s d 0 6 0 2 s , b 0 6 0 2 s , a 0 6 0 2 s c n d, 7 1 , 6 1 9 4 , 8 4 e b t s u m t i . h g i h d e i t e b t o n n a c 8 4 n i p t a h t e t o n . d e t c e n n o c t o n . w o l d l e h r o n e p o s n i p c i f i c e p s c 0 6 0 2 s 1 c t 0 c t 6 1 7 1 r e t t i m s n a r t r o f s n o i t c e n n o c r o t i c a p a c l a n r e t x e . r o t i c a p a c t i m s n a r t l a n r e t x e s i h t f o e u l a v d e d n e m m o c e r e h t . r e t l i f l l p l a n r e t n i e h t , d e r i s e d f i . ) d e s u e b o s l a n a c f n 1 f o e u l a v a ( f n 2 s i r o t i c a p a c . e c n a m r o f r e p n i s s o l o n h t i w d e t t i m o e b y a m r o t i c a p a c l a n r e t x e 0 c r 1 c r 8 4 9 4 r e v i e c e r r o f s n o i t c e n n o c r o t i c a p a c l a n r e t x e . r o t i c a p a c r e v i e c e r l a n r e t x e s i h t f o e u l a v d e d n e m m o c e r e h t . r e t l i f l l p l a n r e t n i e h t , d e r i s e d f i . ) d e s u e b o s l a n a c f n 1 f o e u l a v a ( f n 2 s i r o t i c a p a c . e c n a m r o f r e p n i s s o l o n h t i w d e t t i m o e b y a m r o t i c a p a c l a n r e t x e s a ( n e p o e b t s u m t i . h g i h d e i t e b t o n n a c 8 4 n i p t a h t e t o n . w o l d l e h r o ) r o t i c a p a c l a n r e t x e h t i w d e d n e m m o c e r table 5. pin description and assignment (continued)
8 s2060 gigabit ethernet transceiver march 7, 2001 / revision h table 6. power and ground signals e m a n n i pl e v e l# n i pn o i t p i r c s e d c c v l c ev 3 . 3 +3 2 , 0 2y l p p u s r e w o p e r o c e e v l c ed n g8 5 , 5 2 , 1 2d n u o r g e r o c c c v o i l c ev 3 . 3 +3 6 , 0 6 , 5 5y l p p u s r e w o p o / i l c e p v l e e v o i l c ed n g4 6 , 6 5d n u o r g o / i l c e p v l c c v l t tv 3 . 3 +2 4 , 7 3y l p p u s r e w o p l t t v l d n g l t td n g6 4 , 2 3d n u o r g l t t v l c c v av 3 . 3 +0 5 , 8 1y l p p u s r e w o p g o l a n a e e v ad n g1 5 , 5 1d n u o r g g o l a n a c c vv 3 . 3 +0 1 , 5r e w o p e e vd n g3 3 , 1d n u o r g c n d8 4. h g i h d e i t r o d e t a o l f e b d l u o h s t i . w o l d e i t e b t o n n a c n i p s i h t c n d , 8 2 , 6 2 , 3 5 , 9 2 9 5 , 7 5 . d e t c e n n o c t o n
9 s2060 gigabit ethernet transceiver march 7, 2001 / revision h figure 3. s2060 pinout (S2060A, s2060b, s2060d) 1 2 3 4 5 6 7 8 9 10 11 19 20 21 22 23 24 25 26 27 28 29 62 61 60 59 58 57 56 55 54 53 52 48 47 46 45 44 43 42 41 40 39 38 s2060 top view 37 36 dnc com_det ttlgnd rx[0] rx[1] rx[2] ttlvcc rx[3] rx[4] rx[5] rx[6] ttlvcc rx[7] 35 34 33 rx[8] rx[9] vee 17 18 ewrap eclvcc eclvee tbc eclvcc en_cdet eclvee dnc -lck_ref dnc dnc dnc avcc 30 31 32 rbc1 rbc0 ttlgnd 64 63 txp txn ecliovcc dnc eclvee dnc ecliovee ecliovcc rxp dnc rxn ecliovee ecliovcc 51 50 49 avee avcc dnc 12 13 vee tx[0] tx[1] tx[2] vcc tx[3] tx[4] tx[5] tx[6] vcc tx[7] tx[8] tx[9] 14 15 16 raten avee dnc thermal management e c i v e d x a m e g a k c a p r e w o p q ) r i a l l i t s ( a j q c j ) e g a k c a p s h / p f q p 4 6 m m 0 1 ( a 0 6 0 2 sw 3 3 3 . 1w / c ? 5 4w / c ? 5 1 ) e g a k c a p p f q p 4 6 m m 4 1 ( b 0 6 0 2 sw 3 3 3 . 1w / c ? 5 4w / c ? 5 1 h t i w e g a k c a p p f q p 4 6 m m 4 1 ( d 0 6 0 2 s ) r e d a e r p s t a e h w 5 2 1 . 1w / c ? 0 4w / c ? 5 1
10 s2060 gigabit ethernet transceiver march 7, 2001 / revision h figure 4. s2060 pinout (s2060c) thermal management 1 2 3 4 5 6 7 8 9 10 11 19 20 21 22 23 24 25 26 27 28 29 62 61 60 59 58 57 56 55 54 53 52 48 47 46 45 44 43 42 41 40 39 38 s2060c top view 37 36 rc0 com_det ttlgnd rx[0] rx[1] rx[2] ttlvcc rx[3] rx[4] rx[5] rx[6] ttlvcc rx[7] 35 34 33 rx[8] rx[9] vee 17 18 ewrap eclvcc eclvee tbc eclvcc en_cdet eclvee dnc -lck_ref dnc dnc tc0 avcc 30 31 32 rbc1 rbc0 ttlgnd 64 63 txp txn ecliovcc dnc eclvee dnc ecliovee ecliovcc rxp dnc rxn ecliovee ecliovcc 51 50 49 avee avcc rc1 12 13 vee tx[0] tx[1] tx[2] vcc tx[3] tx[4] tx[5] tx[6] vcc tx[7] tx[8] tx[9] 14 15 16 raten avee tc1 e c i v e dr e w o p x a m e g a k c a p q ) r i a l l i t s ( a j q c j ) e g a k c a p p f q t 4 6 m m 0 1 ( c 0 6 0 2 sw 4 5 1 . 1w / c ? 2 5w / c ? 8 1
11 s2060 gigabit ethernet transceiver march 7, 2001 / revision h figure 5. 10mm x 10mm 64 pqfp package (S2060A) top view
12 s2060 gigabit ethernet transceiver march 7, 2001 / revision h figure 6. 14 mm x 14 mm 64 pqfp package (s2060b) top view
13 s2060 gigabit ethernet transceiver march 7, 2001 / revision h figure 7. 10mm x 10mm 64 tqfp package (s2060c) top view
14 s2060 gigabit ethernet transceiver march 7, 2001 / revision h figure 8. 14 mm x 14 mm 64 pqfp package (s2060d) top view
15 s2060 gigabit ethernet transceiver march 7, 2001 / revision h table 7. power and ground application information n o i t c n u fs e m a n n i ps n o i t c u r t s n i g o l a n a c c v a 0 0 6 ( d a e b e t i r r e f a h g u o r h t y l p p u s v 3 . 3 + d e r e t l i f r o e s i o n w o l o t t c e n n o c w f h l a c o l l a u d e d i v o r p . ) t n e l a v i u q e r o s 1 0 6 b 1 3 m l b a t a r r u m : z h m 0 0 1 t a a . e c n a t s i s e r d n a e c n a t c u d n i w o l r o f ) f p 0 0 1 , f 1 . 0 ( e e v a o t g n i s s a p y b r i a p e h t r o f d e t u t i t s b u s e b n a c r o t i c a p a c f 1 . 0 e c n a t c u d n i w o l e l g n i s . ) e c n a t c u d n i x a m h n 5 . 0 < , t n e l a v i u q e r o 2 1 6 0 j v y a h s i v ( e e v a. e n a l p d n u o r g o t t c e n n o c o / i l c e p v l c c v o i l c e g n i s s a p y b l a c o l l a u d e d i v o r p . v 3 . 3 + o t n o i t c e n n o c e c n a d e p m i w o l e d i v o r p e c n a t c u d n i w o l e l g n i s a r o , l e l l a r a p n i f p 0 0 1 d n a f 1 . 0 ( e n a l p d n g o t . ) r o t i c a p a c f 1 . 0 t n e l a v i u q e r o 2 1 6 0 j v y a h s i v e e v o i l c e. e n a l p d n u o r g o t t c e n n o c e r o c c c v l c e g n i s s a p y b l a c o l l a u d e d i v o r p . v 3 . 3 + o t n o i t c e n n o c e c n a d e p m i w o l e d i v o r p e c n a t c u d n i w o l e l g n i s a r o , l e l l a r a p n i f p 0 0 1 d n a f 1 . 0 ( e n a l p d n g o t . ) r o t i c a p a c f 1 . 0 t n e l a v i u q e r o 2 1 6 0 j v y a h s i v e e v l c e. e n a l p d n u o r g o t t c e n n o c o / i l t t v l c c v l t t g n i s s a p y b l a c o l l a u d e d i v o r p . v 3 . 3 + o t n o i t c e n n o c e c n a d e p m i w o l e d i v o r p e c n a t c u d n i w o l e l g n i s a r o , l e l l a r a p n i f p 0 0 1 d n a f 1 . 0 ( e n a l p d n g o t . ) r o t i c a p a c f 1 . 0 t n e l a v i u q e r o 2 1 6 0 j v y a h s i v e e v l t t. e n a l p d n u o r g o t t c e n n o c
16 s2060 gigabit ethernet transceiver march 7, 2001 / revision h figure 9. power and ground connection diagram 1 16 17 32 33 48 49 64 eclvcc eclvee ecliovee ecliovcc ttlvcc ttlvee avee eclvcc eclvee eclvee ecliovcc ecliovee ttlvcc ttlvee avcc vcc vee vcc vee avcc avee ecliovcc vcc (+3.3 v) v cc (+3.3 v) v cc (+3.3 v) vcc (+3.3 v) v cc (+3.3 v) v cc (+3.3 v) v cc (+3.3 v) v cc (+3.3 v) v cc (+3.3 v) s2060 (top view) 0.1 f 0.1 f 0.1 f 100 pf 100 pf 100 pf ferrite ferrite 0.1 f 100 pf 0.1 f 0.1 f 100 pf 100 pf 0.1 f 100 pf 0.1 f 100 pf 0.1 f 100 pf
17 s2060 gigabit ethernet transceiver march 7, 2001 / revision h figure 10. transmitter timing table 8. s2060 transmitter timing s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 1 c b t . t . r . w p u t e s a t a d2 . 1-s n. 1 e t o n e e s t 2 c b t . t . r . w d l o h a t a d5 2 . 0-s n t r d s t , f d s l l a f d n a e s i r a t a d l a i r e s-0 7 2s p. s i s a b e l p m a s n o d e t s e t , % 0 8 - % 0 2 t j r e t t i j l a t o t t u p t u o a t a d l a i r e s ) p - p ( -2 9 1s p e l p m a s n o d e r u s a e m , k a e p - o t - k a e p 2 r o 5 . 8 2 k h t i w d e r u s a e m . s i s a b 7 1 - . z h g 5 2 . 1 t a n r e t t a p t j d t u p t u o a t a d l a i r e s ) p - p ( r e t t i j c i t s i n i m r e t e d -0 8s p e l p m a s a n o d e t s e t , k a e p - o t - k a e p n r e t t a p 5 . 8 2 k h t i w d e r u s a e m . s i s a b . z h g 5 2 . 1 t a 1. all ac measurements are made from the reference voltage level of the clock (+1.4 v) to the valid input or output data levels (+.8 v or +2.0 v). tbc tx[0-9] t 1 t 2 serial data out figure 11. receiver timing full rate mode (raten active) t 3 t 4 comma t 3 t 4 rbc1 rbc0 serial data in rx[9-0] skew
18 s2060 gigabit ethernet transceiver march 7, 2001 / revision h other operating modes loopback mode the s2060 supports internal loopback mode in which the serial data from the transmitter replaces external serial data. the loopback function is en- abled when the loopback enable signal, ewrap, is set active. the loopback mode provides the ability to perform system diagnostics and to perform off-line testing of the interface to guarantee the integrity of the serial channel before enabling the transmission medium. figure 13 shows the basic loopback operation. output disabled cru csu figure 13. loopback operation figure 12. receiver timing half rate mode (raten inactive) table 9. s2060 receiver timing rbc1 serial data in rx[9-0] t 3 t 4 comma t 3 t 4 s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 3 ) 0 c b r ( 1 c b r e r o f e b d i l a v a t a d0 . 3-s n. 1 e t o n e e s t 4 ) 0 c b r ( 1 c b r r e t f a d i l a v a t a d0 . 2-s n t r c r t , f c r e m i t l l a f d n a e s i r 0 c b r , 1 c b r-4 . 2s n. v 0 . 2 + o t v 8 . + d e r u s a e m w e k sw e k s 0 c b r o t 1 c b r5 . 75 . 8s n. e g d e g n i s i r o t e g d e g n i s i r t r d t , f d e m i t l l a f d n a e s i r t u p t u o a t a d-4 . 2s n. v 0 . 2 + o t v 8 . + d e r u s a e m t k c o l ) p u t r a t s () g 5 2 . 1 ( e m i t k c o l n o i s i u q c a p u t r a t s-5 . 2s t k c o l ) e r i u q c a e r ( ) g 5 2 . 1 ( e m i t k c o l n o i t i s i u q c a a t a d -0 0 1s n e e s ( e y e a t a d t u p n i % 0 9 . ) 9 1 e r u g i f -0 5 2s n. e y e a t a d t u p n i % 4 2 e l c y c y t u d) 0 c b r ( 1 c b r0 40 6% t j e c n a r e l o t r e t t i j t u p n i l a t o t9 9 5-s p. z 3 . 2 0 8 e e e i n i d e i f i c e p s s a t j d e c n a r e l o t r e t t i j t u p n i c i t s i n i m r e t e d0 7 3-s p. z 3 . 2 0 8 e e e i n i d e i f i c e p s s a 1. all ac measurements are made from the reference voltage level of the clock (+1.4 v) to the valid input or output data levels (+.8 v or +2.0 v).
19 s2060 gigabit ethernet transceiver march 7, 2001 / revision h table 11. recommended operating conditions r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a 0 1 0 4 - 2 0 7 1 5 8 2 c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j0 3 1c ? , c c v o i l c e , c c v l c e , c c v l t t n o e g a t l o v e e v / d n g o t t c e p s e r h t i w c c v a d n a 5 3 1 . 33 . 35 6 4 . 3v c b t t p e c x e n i p t u p n i l t t y n a n o e g a t l o v0v c c 0 . 5v n i p t u p n i l c e p v l y n a n o e g a t l o v v c c 0 . 2 - v c c v c b t n o e g a t l o v0v c c v 1. commercial temperature range S2060A, s2060b, s2060c. 2. industrial temperature range s2060d. table 10. absolute maximum ratings r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t e s a c0 4 -5 2 1c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j5 5 -0 3 1c ? e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? d n g o t t c e p s e r h t i w c c v n o e g a t l o v5 . 0 -0 . 4 +v c b t t p e c x e n i p t u p n i l t t y n a n o e g a t l o v5 . 0 -0 . 5v c b t n o e g a t l o v0v c c v n i p t u p n i l c e p v l y n a n o e g a t l o v0v c c v t n e r r u c k n i s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l t t8a m the following are the absolute maximum stress ratings for the s2060 device. stresses beyond those listed may cause permanent damage to the device. absolute maximum ratings are stress ratings only and operation of the device at the maximums stated or any other conditions beyond those indicated in the recommended operating conditions of the document are not inferred. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
20 s2060 gigabit ethernet transceiver march 7, 2001 / revision h table 13. dc characteristics s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c v h o ) l t t ( e g a t l o v h g i h t u p t u o4 . 28 . 2v c c vv c c i , n i m = h o a m 4 = v l o ) l t t ( e g a t l o v w o l t u p t u od n g1 . 04 . 0vv c c i , n i m = l o a m 1 = v h i ) l t t ( e g a t l o v h g i h t u p n i0 . 2v c c v v l i ) l t t ( e g a t l o v w o l t u p n id n g8 . 0v i h i ) l t t ( t n e r r u c h g i h t u p n i0 4a v n i v , v 4 . 2 = c c x a m = i l i ) l t t ( t n e r r u c h g i h t u p n i0 0 6a v n i v , v 0 . 0 = c c x a m = i c c t n e r r u c y l p p u s7 8 15 3 2a m e r a u q s , n e p o s t u p t u o . n r e t t a p p d n o i t a p i s s i d r e w o p0 2 60 2 8w m e r a u q s , n e p o s t u p t u o . n r e t t a p v f f i d g n i w s e g a t l o v t u p n i l a i t n e r e f f i d . n i m s t u p n i l c e p v l l a i t n e r e f f i d r o f 0 0 10 0 2 2v m d v t u o e g a t l o v l a i t n e r e f f i d t u p t u o l a i r e s g n i w s 0 0 2 10 0 0 20 0 2 2v m0 5 1 w . d n u o r g o t c n i e c n a t i c a p a c t u p n i3f p table 12. reference clock requirements s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t fe c n a r e l o t y c n e u q e r f0 0 1 -0 0 1 +m p p d t 2 - 1 y r t e m m y s0 40 6% . t p % 0 5 t a e l c y c y t u d t r c r t , f c r e m i t l l a f d n a e s i r k l c f e r2s n. % 0 8 - % 0 2 j r r e t t i j m o d n a r0 0 1s p. k a e p o t k a e p
21 s2060 gigabit ethernet transceiver march 7, 2001 / revision h output load the s2060 serial outputs require a resistive load to set the output current. the recommended resistor value is 150 w to ground. this value can be varied to adjust drive current, signal voltage swing, and power usage on the board. acquisition time with the input eye diagram shown in figure 19, the s2060 will recover data with a 10e-9 ber within the time specified by t lock in table 9 after an instanta- neous phase shift of the incoming data. t r t f 80% 20% 50% 80% 20% 50% t r t f +2.0 v +0.8 v +2.0 v +0.8 v 150 150 0.01 f 0.01 f 100 0.01 f 0.01 f vcc - 1.3 v bit time amplitude 24% 1.3 normalized amplitude normalized time 1.0 0.0 0.2 0.3 0.5 0.7 0.8 0.1 0.6 0.4 0.3 0.7 0.9 1.0 0.0 figure 17. high speed differential inputs figure 14. serial input rise and fall time figure 18. receiver input eye diagram jitter mask figure 15. ttl input/output rise and fall time figure 16. serial output load figure 19. acquisition time eye diagram
22 s2060 gigabit ethernet transceiver march 7, 2001 / revision h amcc is a registered trademark of applied micro circuits corporation. copyright ? 2001 applied micro circuits corporation d50/r476 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1 ordering information x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i - s0 6 0 2 e g n a r p m e t l a i c r e m m o c ) m m 0 1 p f q p 4 6 ( C a e g n a r p m e t l a i c r e m m o c ) m m 4 1 p f q p 4 6 ( C b n o i t p o s n i p r e t l i f p o o l , e g n a r p m e t l a i c r e m m o c ) m m 0 1 p f q t 4 6 ( C c e g n a r p m e t l a i r t s u d n i ) m m 4 1 p f q p 4 6 ( C d x xxxx x prefix device package

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